Signal processing circuit and information recording/reproducing apparatus using the same, and method for optimizing coefficients of equalizer circuit

ABSTRACT

A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an informationrecording/reproducing apparatus, such as a magnetic disk apparatus and amagneto-optic disk apparatus, and a signal processing circuit used inthose apparatuses, and more particularly to a circuit and a method foroptimizing coefficients of an equalizer circuit having functions ofestimating a detection or discrimination performance in optimization ofthe equalizer circuit, and optimization of various conditions inrecording and reproduction, such as the write current value, DC offsetcompensation amount, etc, in apparatuses involving a partial responseprocessing.

[0002] In an information recording/reproducing apparatus of this kind,it is necessary to optimally set various control parameters forrecording and reproducing signals. To give an example, the optimizationof the write current value in a magnetic disk apparatus is performed asfollows. A write current value is set and recorded on a magnetic disk,then the bit error rate (BER) is measured while varying the phase of thediscrimination window of the phase discriminator, which is a detectioncircuit of the reproduced signal processing circuit, to measure thephase width (phase margin) of the discrimination window which provides atolerable level of BER (e.g., 1.0E−8 or less). FIG. 2 shows a so-calledbucket curve. This measurement is performed each time the write currentvalue is changed, and the phase margins at various write current valuesare obtained. As shown in FIG. 3, the relation between write currentvalues and the corresponding phase margins are checked and the writecurrent value at which the phase margin is greatest is taken as theoptimum value.

[0003] In evaluation of the BER in an apparatus of phase discriminationsystem of this kind, in order to obtain a bucket curve as shown in FIG.2, a length of time at least in the order of minutes is required. Itfollows therefore that several minutes are required only to perform theoptimization of the write current mentioned above.

[0004] In an actual optimization process, in addition to the writecurrent value, other optimization parameters include the compensationamount (in what is referred to as write pre-compensation) of the fluxreversal positions of the write current, equalizer circuitcharacteristics and detection levels of the error detector. Moreimportantly, since those parameters are evaluated using a randompattern, they cannot be evaluated independently of each other. For thisreason, in order to optimize the parameters with high accuracy,measurement of the bucket curve is preferably performed as many times asthe product of the number of parameters and the number of partitions ofthe parameters, so that a vast length of time is required for the wholeoptimization process. If there are great variations among the magneticheads and the recording/reproducing circuits, it is necessary to performthis optimization process for individual apparatuses and magnetic heads,so that a much greater length of time is required.

[0005] In evaluation of the BER by amplitude detection system, on theother hand, the technique disclosed in JP-A-3-144969 is well known. Thismethod is such that a sequence of digital signals input to the detectorof the apparatus are compared with a sequence of reference signals tomeasure a histogram of error values to thereby estimate a BER of theapparatus. The number of bits required to measure the histogram withhigh accuracy is on the order of thousands or tens of thousands at most,and this number is far smaller than one in the above-mentioned case(1.0E+8 bits or greater) using the phase detection system which measuresthe BER directly, and hence the time required to optimize the parametersis much shorter.

[0006] In the evaluation based on the estimation of the BER in theapparatus of amplitude discrimination system revealed in JP-A-3-144969,however, a relatively large scale evaluation device is required formeasuring a histogram of error values. It is required to determine errorvalues in real time and install counters or memories as many as thenumber of the histograms measured. If this measurement of the histogramsis made inside the apparatus, an increase in the scale of the circuit isinevitable. If histograms are measured outside the apparatus whilemonitoring the input signal of the detector on the circuit board,measurement has to be performed at the bit rate of the apparatus, whichposes a great difficulty in mounting or packaging the measuringapparatus in the case of an apparatus adapted to operate at high datatransmission rate exceeding 100 Mbps.

[0007] With regard to the technique of optimizing the tap coefficientsof an equalizer circuit, there is a method disclosed in JP-A-2-150114.In this publication, looking at the fact that the reproduced waveform(so-called solitary magnetization reproduced waveform) which correspondsto a single flux reversal or magnetization reversal in an informationrecording/reproducing apparatus such as a magnetic disk apparatus or amagneto-optic disk apparatus is a waveform that has the leading andtrailing foot portions formed substantially so symmetrically as to besimulated by a Lorentzian waveform, there are proposed coefficientcompensation means and a method of a transversal type equalizer circuitwith symmetric coefficients at three taps, in other words, a so-calledcosine equalizer circuit, wherein in a format on the magnetic disk, atraining area of several bytes is provided before user data to performcoefficient compensation in real time.

[0008] In a case where only one tap coefficient is to be optimized as ina cosine equalizer circuit, it is preferable to use the method disclosedin JP-A-2-150114 mentioned above. However, if data is to be recordedwith high density, the resolution of the reproduced waveformdeteriorates, the foot portions of the waveform trail long, and thesymmetry of the reproduced waveform is disturbed, and consequently asufficient equalizing performance cannot be obtained with a cosineequalizer circuit which roughly adjusts the amplitude characteristicsonly.

[0009] As coefficient compensation algorithms capable of obtainingoptimum values for a plurality of tap coefficients with relatively highaccuracy, sequential compensation type algorithms such as CLMS (clippedleast means square) are well known. However, in an apparatus whichrestores a clock signal for an equalizer circuit from a signal obtainedat the subsequent stage of the equalizer circuit, contention occursbetween the phase characteristic of the equalizer circuit and clockphase due to tap coefficients of the equalizer becoming asymmetric inthe coefficient compensation process, and because of this, thecharacteristics of the equalizer circuit do not settle. Moreover, aproblem arises that the coefficients in the converged state unavoidablyoscillate due to the delays of the equalizer circuit and the coefficientcompensation circuit portion and also due to the effects of the finitebit number of the digital circuit, and for this reason, a sufficientperformance cannot be obtained.

[0010] To execute the above-mentioned coefficient compensationoperation, the head disk controller needs to cause the read gate to openwhen the head is located over a data area, and for this purpose at leastID must be able to be read even under a condition that the equalizercircuit is not in the optimized state. Therefore, it is required that adata pattern (a sync byte in this case) to demarcate an area for usewith AGC/PLL from a data area be formed in a specific pattern easy toidentify.

[0011] Furthermore, if a signal processing circuit is designed as a LSI,the scale of the circuit becomes large-size, so it is important to takeinto consideration the chip area, power consumption, the number of pins.cost, etc. It is desired that all components be packaged in a one-chipLSI. However, if power consumption is large, for instance, the signalprocessing circuit needs to be formed in two or more subdivided chipsand hence it is important at what portion the circuit is to be divided.

SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide ahigh-performance small-scale signal processing circuit, whichcompensates the amplitude characteristics with high accuracy and alsocompensates the phase characteristics by a combination of a sequentialcompensation type coefficient compensation circuit and an equalizercircuit, and provide an information recording/reproducing apparatususing the above-mentioned signal processing circuit.

[0013] Another object of the present invention is to provide a methodand an apparatus for optimizing various control parameters, which enablethe optimization of various control parameters of an informationrecording/reproducing apparatus in a relatively short time.

[0014] Yet another object of the present invention is to provide a moreefficient LSI configuration when implementing a reproduced signalprocessing circuit by subdividing it into LSIs of a plurality of chips.

[0015] The above objects of the present invention are achieved by asignal processing circuit including an equalizer circuit and asequential compensation type coefficient circuit, configured asdescribed in the following.

[0016] This signal processing circuit uses a transversal type equalizercircuit with five or more taps, and of the tap coefficients of theequalizer circuit, the tap coefficients adjacent on both sides to thecenter tap are specified at the same value. Results of simulation by thepresent inventors showed that when the same value is set for the tapcoefficients adjacent on both sides to the center tap, even if the twotaps at the extreme ends on both sides are left free, contention withthe phase characteristics of the PLL can be avoided, and even if thecoefficient compensation circuit is of the sequential compensation type,the coefficient compensation process can proceed stably. The reason isthat even when a signal input to the equalizer circuit has a phasedistortion, since at least the two coefficients at the extreme end tapson both sides take different values, the waveform distortion afterequalization can be minimized.

[0017] At this time, the phase distortion of the signal appears as thefront-back symmetry Tas of a solitary waveform, and if the Tas isdefined as

Tas=T1−T2/PW50

(PW50=T1+T2),

[0018] According to the present invention, even when Tas=11%, anequalizing performance substantially equivalent to a Wiener filter (anoptimum filter for minimizing the square error) can be obtained. Withregard to the symbols in the above equation, PW50 is a mesial pointwidth, the leading edge of PW50 is designated by T1 and the trailingedge is designated by T2. According to the simulation results, if aratio S of the mesial point width PW50 of a signal input to theequalizer circuit to a data period Tb (this ratio S is called a channeldensity) is

S=PW50/Tb>2,

[0019] the tap number of the equalizer circuit is preferably seven orlarger. If the tap number is five, errors are large at the output of theequalizer circuit, so that a good apparatus performance cannot beobtained. In this case, too, of the tap coefficients of the equalizercircuit, only the tap coefficients adjacent on both sides to the centertap are specified at the same value and hence the other four taps on thefarther positions on both sides may take different values.

[0020] In the present invention, in a transversal type equalizer circuitwith five or more taps, of the tap coefficients of the equalizercircuit, not only those adjacent on both sides to the center tap butalso those at the positions symmetric with respect to the center tap arepreferably, in some cases, at the same value. This is because if thereis a good symmetry in the impulse response of signals input to theequalizer circuit, equalization with high accuracy is possible even witha low resolution. Accordingly, in addition to the effect that nocontention of phase characteristics occurs as described above, anothereffect is that coefficient compensation is carried out for all taps byan average or mean correlation signal of two bits at respective tappositions, so that the magnitude of noise of the input signal can bereduced to about 0.7 times the original magnitude and for this reason,coefficient compensation can be performed with good stability.

[0021] Further, in the present invention, in an application using atransversal type equalizer circuit, negative coefficient values of theequalizer circuit should preferably be able to be set with positivecoefficient values by inverting the output of tap delay means. As in areproduced waveform of a solitary magnetization in magnetic recording,in the case of a waveform with its foot portions lowering in arelatively monotonous form, the tap coefficients of a transversal typeequalizer circuit for equalizing this waveform change their signsalternately in a sequence of minus, plus, minus, plus and so on towardsboth ends if the sign of the coefficient at the center tap is plus.Therefore, it is possible to output data by inverting data at the tappositions which can be estimated to be negative coefficients.Consequently, the signs of the coefficient bits of the equalizer circuitcan be omitted and thus the scale of the circuit can be reduced.

[0022] In the present invention, the tap coefficients are preferably setin registers. A coefficient value “0” is set at specific tap positionsof the transversal type equalizer circuit and the coefficientcompensation operation is stopped. By this arrangement, it is possibleto perform the most desirable form of coefficient compensation when asmall tap number is set, and furthermore power consumption is reduced atthe taps with coefficients of “0”.

[0023] An input signal to the equalizer circuit is preferably input tothe coefficient compensation circuit after it is processed into apartial response waveform, for example. By so doing, the accuracy of thecoefficient compensation circuit can be improved, coefficientcompensation using a rather random, arbitrary data pattern becomespossible, and this compensation operation can be carried out at the usersite. For example, even when the characteristics of the magnetic head ordisk medium change with time in a magnetic disk apparatus, the optimumequalizer circuit condition can be maintained at all times on theapparatus.

[0024] The coefficient compensation of an equalizer circuit according tothe present invention is performed by using the following means. To bemore specific, the coefficient compensation circuit includes simplifieddetection means for roughly discriminating an input signal of theequalizer circuit, error calculating means for calculating an errorsignal from an output signal of the equalizer circuit and the simplifieddetection means, delay means for delaying the output signal of thesimplified detection means, correlation value calculating means forcalculating a correlation value between the output signal of the delaymeans and an output signal of the error calculating means, correlationvalue adding means for sequentially adding output signals of thecorrelation value calculating means, delta-value calculation means forcalculating a coefficient compensation amount from a signal obtained byadding output signals of the correlation value adding means a certainnumber of times, and coefficient error compensating means forcompensating the coefficient values of the equalizer circuit by anoutput signal of the coefficient compensation amount calculating means,wherein the coefficient compensation circuit is stopped from performinga sequential addition of correlation values for a delay time after thecoefficient compensation is executed until the signal input to theequalizer circuit is output or longer.

[0025] According to the above arrangement, correlation data is notobtained while the coefficients are being compensated and thecorrelation data is accumulated using fixed tap coefficient value at alltimes. Therefore, the coefficient compensation circuit according to thisarrangement does not allow errors to occur which used to occur due to aloop delay in the conventional CLMS (clipped least mean square) step. Inaddition, this coefficient compensation circuit is basically a open loopand therefore can perform signal processing steps sufficiently, whichincludes averaging (corresponding to the operation of the correlationvalue calculating means in this arrangement), and can reduce the effectsof the finite bit number or the like, and high hopes can be held on thiscoefficient compensation circuit for compensation with improvedaccuracy.

[0026] The above-mentioned coefficient compensation circuit may furtherinclude delay time control means for controlling the amount of delay ofthe delay means, selection means for selecting a tap coefficient to becompensated, in an interlocked manner with the delay time control means,and coefficient temporary holding means for temporarily holding a tapcoefficient value compensated by the coefficient error compensatingmeans, wherein the delay time may be a fixed amount when the tapcoefficient compensation amounts are calculated and all tap coefficientsmay be compensated when respective tap coefficient values have beendecided by controlling the selection means. The coefficient compensationmeans according to the present invention is formed basically in a openloop, as stated above. Therefore, if it is possible to guarantee thelinearity and the randomness of a signal input to the equalizer circuit,respective tap coefficients need not be compensated by the sameinformation (signal). The tap coefficients can be compensated in a timesharing manner, and for this reason the circuit scale can be reduced ina great measure.

[0027] Further, in the above-mentioned arrangement, an input signal tothe equalizer circuit, which also is an input signal to the coefficientcompensation circuit of the equalizer circuit, and an output signal fromthe equalizer circuit can be input after they are both decimated. As hasbeen described, in the coefficient compensation means, it is onlyrequired to receive error signals between an input signal and an outputsignal of the equalizer circuit, which correspond to the tapcoefficients. Therefore, the error signals between the input signal andoutput signal of the equalizer circuit need not necessarily be obtainedcontinuously, but may be decimated as mentioned above. By decimation,the operation frequency of the coefficient compensation circuit can bereduced to 1/(decimation number+1), so that the power consumption can bereduced to a great extent without increasing the scale of the circuit.

[0028] As means for external calculation of the optimum coefficientvalue, data holding means may be provided to hold, in step with the dataclock, signals supplied to the transversal type equalizer circuit foreach data segment having at least twice the number of all taps of theequalizer circuit, and output the data held therein by clock means otherthan the data clock. As for means for obtaining tap coefficients of theequalizer circuit other than the above-mentioned sequential compensationcircuit, there is a method of storing a considerable amount of the inputsignal to the equalizer circuit serially, and giving an ideal outputcorresponding to the stored input signal to thereby obtain a generallywell-known Wiener filter solution. By using this method, it is possibleto transfer the stored data to the outside and obtain the optimumsolution by a matric operation. The data segment length can be reducedto about twice the number of taps of the equalizer circuit by makingcontrivance to the data pattern or the like. Note that a longer datasegment makes the effects of noise smaller, making it possible to obtainbetter tap coefficients.

[0029] According to the present invention, as a circuit for optimizingthe parameters, an error detection circuit can be formed as described inthe following.

[0030] For example, an error detection circuit includes errorcalculating means for calculating an error signal in a (second)detection circuit from the input signal supplied to the (second)detection circuit and the output signal from the (second) detectioncircuit, distinction means for outputting a count signal when an errorsignal is larger than a preset threshold value; and counting means forcounting the count signals. An error signal between the input signal tothe detection circuit in the signal processing circuit and the targetamplitude of the equalizer circuit is obtained by the (second) detectioncircuit and the error calculating circuit. This error signal is comparedwith the fixed threshold value set on the distinction circuit, and whenthe error signal is equal to or larger than the threshold value, adistinction output is set to “1”, or otherwise the distinction outputgoes to “0”. The above-mentioned counting means increments only when thedistinction means produces a “1” output.

[0031] The input signal and the error signal of the above-mentioneddetection circuit occur as shown in FIG. 4, and the error signal isdistributed over positive and negative sides with “0” at the center ofdistribution and is therefore regarded as substantially a normaldistribution. Hence, the ratio of the count value to a total populationparameter is decided by the variance value of the error signals and theabove-mentioned fixed threshold value of the distinction means. In otherwords, because the total population parameter and the threshold valueare known, the variance value of the error signal can be estimated bythe count value. Generally, the performance (BER) of the detection meansin the apparatus depends on the quality (the variance value, forexample) of signal input to the detection means. Therefore, byminimizing the variance value, the various parameters of the apparatuscan be optimized.

[0032] In the above-mentioned error detection circuit, the detectionlevel of the (second) detection circuit may be set by using a register.If it is so arranged that the detection level of the (second) detectioncircuit in the error detection circuit can be set arbitrarily, errordetection is possible with the threshold value being varied and thisoffers the following advantages. Normally, the (second) detectioncircuit has binary detection levels of +0.5 and −0.5 to detect ternarylevels of +1, 0 and −1. For example, if the output data pattern of theequalizer circuit to be detected is a data pattern which can take onlytwo values of +1 and −1, detection errors are likely to occur dependingon the magnitude of errors and noise at the above-mentioned detectionlevels. In this case, if the threshold value is set at “0”, thedetection circuit can be made to operate as a substantially binarydetection circuit, which means that the detection performance isimproved (the antinoise performance is improved twice as high) and theerror signals can be detected to a more accurate value, so that a moreaccurate optimization of the apparatus can be achieved.

[0033] Further, in the above-mentioned error detection circuit, thedetection level of the (second) detection circuit can be set by aregister. If the (second) detection circuit can be operated as abinary-output type detection circuit which has one threshold value, thedetection performance can be improved (the antinoise performance isimproved twice higher than in the prior art) with respect to a specificdata pattern and accordingly error signals can be detected to a moreaccurate value. If the output of the (second) detection circuit is keptat “0” at all times, the output value of the equalizer circuit can beinput directly to the distinction means.

[0034] Further, the above-mentioned error detection circuit may be usedalong with a register or the like, as described in the following. Togive an example, the signal processing circuit may be added with a writecurrent setting register and a write current output terminal. Therelation between the write current value of the recording head in aninformation recording/reproducing apparatus and the amplitude of thereproduced output input to the signal processing circuit issubstantially as shown in FIG. 5. Generally, the larger the amplitude ofthe reproduced output detected by the reproducing head is, the betterthe quality of the reproduced signal becomes. At this time, if the inputsignal to the detection means of the signal processing circuit is asignal corresponding to a pattern of . . . +1, +1, −1, −1, +1, +1 . . ., the typical signal amplitude is made to have only two levels ofpositive and negative equalization target values by the automatic gaincontrol circuit, providing no level corresponding to “0”. Because theratio of noise to a signal is larger for a smaller reproduced outputamplitude, the variance of the error signals input to the distinctionmeans is greater as shown in FIG. 5. Therefore, if the error signals arejudged by a suitable negative threshold value and the occasions that anerror signal is higher than the threshold value are counted each timethe write current value is changed, it will be known that the writecurrent value at which the count value (the number of counts) isgreatest is the optimum condition.

[0035] According to the present invention, the signal processing circuitmay include therein a register to set a sense current value of thereproducing head and a sense current output terminal. When amagnetoresistive effect element is used for the reproducing head of aninformation recording/reproducing apparatus, if the bias magnetizationby the head is not optimized, the amplitude of the reproduced waveformvaries depending on the polarity of solitary magnetization. Solitarywaveforms are input to the signal processing circuit through ACcoupling, the signal to the detection circuit signal shifts with respectto the “0” level as shown in FIG. 7. Therefore, data is recorded in arecording pattern such that the magnetization density on the recordingmedium is lowest, and errors are detected each time the sense currentvalue is changed, as follows.

[0036] The output of the (second) detection circuit is maintained at “0”at all times, the output of the equalizer circuit is input directly tothe distinction means and the threshold value of the distinction meansis set at “0”, and each time the sense current value is changed, theoccasions that the threshold value “0” is exceeded for a fixed period oftime are counted. When the bias magnetization by the sense current isnot optimized and the amplitude ratio varies, the mean value of theerror signal shifts from “0”, so that the count value does not become ½of a total population parameter. The sense current at which the shift atthis time from “0” is less than the reference value and the count valueobtained by a fixed negative threshold value is greatest is taken as theoptimum sense current.

[0037] Further, the signal processing circuit may include therein anoffset setting circuit for DC offset compensation and an offsetcompensation register, and the offset amount may be compensated from theno signal condition.

[0038] By making arrangement such that the output signal of theequalizer circuit comprises only random circuit noise and detectingerrors each time the setting value of the offset compensation amount ischanged, the offset compensation amount at which the shift of the meanvalue of the error signals of equalizer circuit output from “0” issmallest is taken as the optimum offset compensation amount.

[0039] Note that in a signal processing circuit of the sameconfiguration as mentioned above, the offset amount may be compensatedfrom a single-frequency signal.

[0040] By recording data of a single recording frequency and bydetecting errors each time the offset compensation amount setting ischanged, the offset compensation amount at which the error variance ofequalizer circuit output is smallest is taken as the optimum offsetcompensation amount.

[0041] In the present invention, in the signal processing circuitmentioned above, coefficient registers to give desirable characteristicsto the equalizer circuit are provided. By using recorded data in arandom form and detecting-errors each time the coefficient value settingis changed, the coefficient value at which the error variance ofequalizer circuit output is smallest is taken as the optimum offsetcoefficient value.

[0042] A register for a compensation value of the write pre-compensationcircuit to compensate the flux reversal positions during recording dataaccording to a sequence of data may be used. By using random data forrecording, and detecting errors each time data is recorded with thevalue setting changed in the compensation value register, the writepre-compensation value at which the error variance of equalizer circuitoutput is smallest is taken as the optimum compensation value.

[0043] In another embodiment of the error detection circuit in thepresent invention, the error detection circuit may be formed to includedistinction means to receive an input signal which is also supplied asan input signal to the detection circuit and output a count signal whenthe input error-signal is larger than a threshold value; counting meansfor counting count signals output from the distinction means; and meansfor setting the threshold value. By arranging such that the outputsignal of the equalizer circuit (the input signal to the detectioncircuit) comprises only circuit noise in substantially random form anddetecting errors each time the offset compensation amount setting ischanged, the offset compensation amount at which the shift of the meanvalue of the error signals of output of the equalizer circuit from “0”is smallest is taken as the optimum offset compensation amount.

[0044] Adjustment of the offset compensation value and optimization ofthe sense current of the magnetoresistive effect type reproducing headcan be performed without the (second) detection circuit. A signalprocessing circuit to enable these operations includes first distinctionmeans for receiving an input signal which is also supplied to thedetection circuit and outputting a count signal when the input errorsignal is less than the threshold value; first counting means forcounting count signals from the first distinction means; seconddistinction means for outputting a count signal when the input errorsignal is larger than the threshold value; second counting means forcounting count signals from the second distinction means; count valuecalculating means by subtracting the count value of the second countingmeans from the count value of the first counting means; and means forsetting the threshold value.

[0045] According to this circuit, by using output signals from theequalizer circuit to directly count errors, it is possible optimize theoffset adjustment and the sense current of the magnetoresistive effecttype reproducing head.

[0046] Note that in this circuit, out of the input signals to thedetection circuit, the signals from which sign bits have been removedmay be accepted as input signals. If the sign bits are removed from theinput signals to the detection circuit (output signals from theequalizer circuit), the negative input signals are converted intopositive signals and the originally positive input signals remainunchanged (when the original signals are expressed in 2s compliments).When the output signals of the equalizer circuit are of a singlefrequency type like +1, +1, −1, −1, +1, +1, −1, −1 and so on, thesignals from which the sign bits have been removed are converted asshown in FIG. 7. Therefore, by setting the threshold value of thedistinction means in the neighborhood of the target value ofequalization of the equalizer circuit, the variance of errors can bedetected.

[0047] Further, in the circuit mentioned above, it is possible toprovide two modes; a first mode to accept the signals from which signbits have been removed out of all input signals to the detectioncircuit, and a second mode to accept the sign bits too and the two modescan be selected by using registers. This arrangement makes the circuitsimpler than in the case where the detection circuit is used, and theoffset compensation amount, the write current and the optimum sensecurrent can be obtained by substantially the same method.

[0048] Further, to improve the reliability of recording and reproductionof a specific data pattern necessary to optimize the above-mentionedparameters, it is possible to reset the pre-coding means just before async byte which indicates the start of a data division when recordingdata. By so doing, the magnetized condition of the data pattern from thesync byte onwards can be specified, and the specific pattern necessaryto optimize the above-mentioned parameters can be recorded.

[0049] If the present invention is considered a recording method forcausing a flux reversal to occur at data “1” and maintaining the writecurrent direction at data “0”, such means is used as using a sync bytewhich starts with “0” at the leading end of data and has no successivedata “1” in a sequence of serial data. By this arrangement, it ispossible to provide a sync byte which precludes interference with a datapattern written in advance for the AGC and PLL circuits and providesless chances of non-linear distortion in recording. Therefore, the writecurrent, sense current and equalizer coefficients can be detected withrelative ease even if they are not optimized.

[0050] Further, in addition to the above arrangement, the sync byte isformed such that the sync byte's record code data having a sequence ofdata “0” and “1” differs for more than ½ of a byte from a sequence ofdata “0” and “1” recorded before the sync byte. Consequently, it ispossible to greatly reduce the probability of mistakenly detecting thedata pattern for the AGC and PLL circuits written in advance as if it isa sync byte.

[0051] Further, in the present invention, to realize a signal processingcircuit less subject to degradation, the target amplitude value of anautomatic gain control circuit (AGC) is varied according to set valuesin registers. By this arrangement, when the resolution of input signalis low, by using a smaller target amplitude value, signals are preventedfrom being saturated in some parts of the signal processing circuit and,for example, impulse noise can be prevented from affecting signalprocessing. When the resolution of input signal is high, by increasingthe target amplitude value, degradation attributable to the circuit suchas circuit noise can be reduced and the BER can be improved.

[0052] Further, in the present invention, in a signal processing circuitincluding a mixture of analog and digital circuits, in which the controlcircuits of the AGC and the PLL are formed as digital circuits, theentire circuit is formed as a two-chip LSI including analog and digitalchips, and outputs of the control circuits of the AGC and the PLL on thedigital chip are supplied through current-output type D/A convertercircuits via pin terminals to a variable gain amplifier (VGA) and avoltage controlled oscillator (VCO) on the analog chip. In this way, bysupplying output data from the digital chip in the form of a current,the influence of noise which may enter the signals from the digital chipitself can be reduced, and the number of pins required can be madesubstantially smaller than in the case where those signals are output inthe form of a digital signal of several-bit codes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0053]FIG. 1 is a diagram showing an embodiment of the present inventionin which the present invention is applied to a magnetic disk apparatus;

[0054]FIG. 2 is a diagram showing measurement results of the phasemargin of the magnetic disk apparatus;

[0055]FIG. 3 is s diagram showing a method for deciding an optimum writecurrent according to the measurement results of the phase margin of themagnetic disk apparatus;

[0056]FIG. 4 shows a histogram of the identification circuit accordingto the present invention and a histogram of error signal;

[0057]FIG. 5 shows a diagram showing the amplitude of reproduced outputaccording to the write current and diagrams showing error distributionsaccording to magnitudes of error signal;

[0058]FIG. 6 shows waveforms of input to the signal processing circuitwhen the amplitude differs due to solitary waves of differentpolarities;

[0059]FIG. 7 is a diagram showing signal conversion by removal of thesign bits;

[0060]FIG. 8 is diagram showing the equalizer circuit and thecoefficient compensation circuit in the embodiment of the presentinvention;

[0061]FIG. 9 is a diagram showing a modification of the equalizercircuit in the embodiment of the present invention;

[0062]FIG. 10 is a diagram showing another embodiment of the equalizercircuit in the embodiment of the present invention;

[0063]FIG. 11 is a diagram showing detail of the coefficientcompensation circuit in the embodiment of the present invention;

[0064]FIG. 12 is a diagram showing a modification of the coefficientcompensation circuit in the embodiment of the present invention;

[0065]FIG. 13 is a diagram showing another embodiment of the coefficientcompensation circuit in the embodiment of the present invention;

[0066]FIG. 14 is a diagram showing a modification of the coefficientcompensation circuit in the embodiment of the present invention;

[0067]FIG. 15 is a diagram showing the error detection circuit in theembodiment of the present invention;

[0068]FIG. 16 is a diagram showing a modification of the error detectioncircuit in the embodiment of the present invention;

[0069]FIG. 17 is a diagram showing a modification of the error detectioncircuit in the embodiment of the present invention;

[0070]FIG. 18 is a diagram showing a modification of the error detectioncircuit in the embodiment of the present invention;

[0071]FIG. 19 is a diagram showing a modification of the error detectioncircuit in the embodiment of the present invention;

[0072]FIG. 20 is a diagram showing a modification of the error detectioncircuit in the embodiment of the present invention;

[0073]FIG. 21 is a diagram showing the sync byte detection circuit inthe embodiment of the present invention;

[0074]FIG. 22 is a diagram for explaining the sync bite detectioncircuit in the embodiment of the present invention; and

[0075]FIG. 23 is a diagram showing another embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0076] Preferred embodiments of the present invention in which thepresent invention is applied to a magnetic disk drive will be describedwith reference to the accompanying drawings.

[0077] In FIG. 1, a magnetic disk drive (HDD) 7 according to anembodiment of the present invention is made up of seven main functionblocks, including a head disk assembly (HDA) 1, a write signalprocessing circuit (WSPC) 2, a reproduced signal processing circuit(RSPC) 3, a signal processing interface (SPIF) 33, a head diskcontroller (HDC) 4, a servo signal processing circuit (SRVC) 5, and anapparatus controller (CNT) 6. For this apparatus, for example, aso-called PRML system is adopted which uses partial response class 4(PR4) and maximum likelihood (ML) decoding (also known as Viterbidetection).

[0078] Each of the above-mentioned components will be described.

[0079] The HDA 1 includes a reproducing head (MR head) 8 employing amagnetoresistance effect element, a thin-film recording head (IND head)9, a read/write preamplifier (R/W IC) 11, and a magnetic disk (DISK).When recording information, a write current which is reversed accordingto information from WSPC 2 is supplied through R/W IC 11 to IND head 9and recorded as magnetized information on DISK 10 rotating at a fixedrotating speed. In reproduction, feeble magnetized information detectedby MR head 8 is amplified by R/W IC 11 and output to RSPC 3. It is to benoted that the magnitudes of the write current of IND head 9 and thesense current of MR head 9 are controlled by WSPC 2 and RSPC 3, and thatthe rotation of DISK 10 and positioning of IND head 9 and MR head 8 onDISK 10 are controlled by SRVC 5.

[0080] WSPC 2 includes a modulator circuit (ENC; encoder) 15 and aparallel/serial data converter circuit (P/S) 14, a writepre-compensation circuit (WPC) 12, a pre-coder (PRE CODER) 13,synthetizer (WVCO; write voltage controlled oscillator) 16, and a Iw(write current) setting circuit (IWC) 60. Write information from HDC 4is converted into a form of information suitable for magnetic recordingby ENC 15, then further converted by P/S 14 into a serial bit sequence,and precoded by PRE-CODER 13. The write current, after having itsreversal positions compensated by WPC 12 so that the sequence of bits berecorded at specified positions, is output to HDA 1. Note that theoutput current value of IWC 60 is controlled by registers (RGIF) of SPIF33. ENC 15 monitors record information from HDC 4, and each time a syncbite immediately after a preamble and immediately before user data isdetected, resets PRE-CODER 13 just before the SYNC byte so that the syncbytes can be recorded in the same magnetized pattern at all times.

[0081] RSPC 3 includes an automatic gain control circuit (AGC) includinga variable gain amplifier circuit (VGA) 17, an amplitude control circuit(ACC) 29 including an amplitude value detection circuit, and a D/Aconverter DAC (VDAC) 30 for a current output type; an automatic phaselock loop (PLL) including a voltage controlled oscillator (RVCO) 28, aphase control circuit (PCC) and a D/A converter DAC (PDAC) 27 for acurrent output type PLL, a programmable filter (LPF) 18, an A/Dconverter (ADC) 19, a digital transversal type equalizer (TREQ) 20, a(1+D) processing circuit 21, a detection circuit or maximum likelihooddecoder (ML) 22, a serial/parallel data converter (S/P) 23, ademodulator circuit (DEC) 24, and a sync byte detection circuit (SYNCDET) 25. RSPC 3 further includes a coefficient compensation circuit(CCOMP) 31, an error detector or counter (ERRC) 32, and a Is (sensecurrent) setting circuit (ISC) 61. The target amplitude of ACC 29 is setby registers in SPIF 33. The present invention is characterized by theconstitutions of CCOMP 31, ERRC 32 and TREQ 20 and the relation amongthose components.

[0082] In an ordinary reproducing operation, the reproduced signal fromHDA I is equalized into the output waveform of PR 4 as it passes throughVGA 17, LPF 18, ADC 19, TREQ 20, and (1+D) 21. Simultaneously with this,the AGC control works so that the output of (1+D) 21 has a fixed signalamplitude, and likewise, the PLL control works so that a sampled phaseof output of (1+D) 21 is correct. Moreover, the waveform of PR 4 isdiscriminated by ML 22, and the output is restored to the recorded userdata as it passes through S/P 23 and DEC 24. SYNC DET 25 fixes theconversion timing of S/P 23 when it detects the sync byte mentionedabove.

[0083] The detailed constitution of TREQ 20 and the constitution andoperation of CCOMP 31 and ERRC 32 will be described later. In thisembodiment, TREQ 20 and ML 22 are formed by digital circuits, but thepresent invention can be applied to signal processing circuits using ananalog equalizer and an analog ML. However, digital ones are morepractical and preferable, one reason for which is the ease of adjustmentby arithmetic operations. Hereafter, description will be made chiefly ofembodiments in which those circuits of digital type are adopted. LPF 18may or may not have a booster mechanism.

[0084] SPIF 33 includes a scrambler or descrambler, an interface circuitwith HDC 4, and a register interface (RGIF) 34 with various circuits.This circuit block transfers data to be recorded or data reproduced toand from HDC 4 in ordinary recording and reproduction. Further, SPIF 33sets or outputs the register values of the above-mentioned variouscircuit blocks through interaction with CNT 6.

[0085] HDC 4 includes an error correction circuit (ECC), etc. User datais added with ECC code and recorded on DISK 10 as record data, and theECC is also reproduced together with the user data. By using thereproduced ECC, errors in the user data are detected and corrected.

[0086] SRVC 5 includes a servo position information peak holding circuit(P/H), a head seek and disk rotation control circuit (SCNT) 36, and aservo driver (SDRV) 35. In response to commands from CNT 6, SRVC 5analyses the reproduced waveform of LPF 18 and controls head seek anddisk rotation.

[0087] CNT 6 includes controlling of a communication control (BUSC) forcontrolling communications with apparatus bus, and also includescontrollings of HDA 1, WSPC 2, RSPC 3, SRVC 5, and so on. Chiefly inaccordance with write and read commands from a host computer to whichthe magnetic disk apparatus (HDD) according to this embodiment isconnected, CNT 6 controls the circuit blocks in HDD 7.

[0088] In this embodiment, of those circuits, all of WSPC, RSPC and SPIFand a part of SRVC are included in the signal processing LSI (SPLSI) 38.

[0089] With reference to FIG. 8, the constitutions of the equalizer 20and the coefficient compensation circuit 31 will be described.

[0090] A register 42 for setting tap coefficients in the equalizer(TREQ) 20 will first be described. In the seven-tap transversal typeequalizer (TREQ) 20, of the tap coefficients of the equalizer 20 (K0,K±1, K±2, K ±3), the center tap (K0) has its coefficient fixed at K0=“1” and the tap coefficients (K±1) adjacent on both sides to the centertap are set at the same value (K+1 =K−1) and therefore a common registeris used. Note that the embodiment in FIG. 8 is described using a case ofseven taps as an example, but as has been described, the number of tapsmay be any number from five or greater. In this embodiment, seven tapsare used in anticipation of such an occasion that the channel density ofsignals to be input to the equalizer is S=PW50/Tb>2. Reference numeral39A denotes delay elements, 40A denotes multipliers and 41A denotes anadder. Obviously, it is possible to add together two data at tappositions corresponding to the same tap coefficient and then multiplythe output of ADC by the sum of those data in one multiplier.

[0091] The coefficient compensation circuit (CCOMP) 31 includes asimplified detection circuit (SDET) 43 for outputting only plus andminus signs of the respective bits of the input signal (ADC output) tothe equalizer (TREQ) 20; a detection circuit (DET) 44, formed by acomparator, for example, to receive the output signal from (1+D) 21 asan input signal; an adder 41B working as an error calculating circuitfor calculating an error signal e from input and output signals of thedetection circuit 44; delay elements (DLY) 39B for delaying the outputsignal of the simplified detection circuit (SDET); and a delta-valuecalculation circuit for new coefficients (DELTACAL) 45 for compensatingthe coefficient compensation amount from a correlation value between theoutput signal of the delay elements 39B and the output signal e of theerror calculating circuit 41B. The output signals of the delay elementscorresponding to the tap coefficients K+1 and K−1 are added together bythe adder 41C and input to the DELTACAL's 45.

[0092] Description will now be made of the operation of the equalizer(TREQ) 20 and the coefficient compensation circuit (CCOMP) 31 incoefficient compensation. The coefficient compensation circuit (CCOMP)31 is used to compensate tap coefficients of TREQ 20 so that PR4(partial response class 4 equalization) can be done accurately by outputof the (1+D) 21, but this CCOMP 31 is not operated in an ordinaryreproduction process.

[0093] The coefficient compensation is carried out by the followingprocedure. A random-like data pattern is recorded in a proper area onthe magnetic disk. Then, with CCOMP 31 put into operation, thisrandom-like data pattern is reproduced. Consequently, the input signal(ADC output signal) to the equalizer circuit 20 and the signal suppliedfrom the equalizer circuit 20 and processed by the 1+D circuit (namely,the 1+D output signal) are input sequentially into the CCOMP 31. The ADCoutput signal is coded by SDET 43 and the output is shifted by the delayelements 39B sequentially. At this time, the error signal e calculatedby the detection circuit 44 and the adder 41B and output of the delayelements 39B are input to the DELTACAL's 45, thereby correcting the tapcoefficients of the coefficient registers 42. The tap coefficients ofthe TREQ 20 are compensated sequentially while the CCOMP 31 is inoperation.

[0094] At this time, of the tap coefficients of the equalizer 20, thetap coefficients (K±1) adjacent on both sides to the center tap havegreat influence on the amplitude characteristics and the phasecharacteristics. If the coefficients are set to allow K+1≠K−1 in theprocess of sequential coefficient compensation, the equalizer 20 itselfassumes phase characteristics. In consequence, the locked phase(sampling timing of ADC 19) of the automatic phase lock circuit (PLL)shown in FIG. 1 suffers a phase shift. The coefficient compensationcircuit (CCOMP) 31 now decides the phase characteristics regardless ofthe PLL, so that the phase characteristics are not fixed and thecoefficient values decided by CCOMP 31 do not become stable. If thesampling timing is shifted excessively, errors at the output of theequalizer increase, and when the balance between the tap coefficientsK+1 and K−1 is disturbed too much, the phase of the PLL is unlocked.

[0095] According to this embodiment, as a condition of K+1=K−1 is added,changes of the phase characteristics hardly occur which would be causedby an imbalance of the tap coefficients of the equalizer in thecoefficient compensation process. Consequently, contention with thephase characteristics of the automatic phase lock circuit is avoided,making it possible to perform coefficient compensation with highaccuracy even with a coefficient compensation circuit of the sequentialcompensation type. The arrangement for the coefficient of the center tapto be fixed at “1” is also instrumental in avoiding the contention withthe automatic gain control circuit (AGC).

[0096] As the algorithm for coefficient compensation, for example, agenerally known CLMS (clipped least mean square) can be used.

[0097] A modification of the equalizer 20 in the present invention willnow be described with reference to FIG. 9.

[0098] In this modified embodiment, a seven-tap transversal typeequalizer 20 is used. Of the tap coefficients in the coefficientregister 42 of the equalizer 20, the tap coefficients (K+1 and K−1, K+2and K−2, K +3 and K−3) at positions symmetric with respect to the centertap are arranged to have the same value. Data at the latter-half tappositions are added with data at the former-half tap positions by adders41C and are input to multipliers 40A.

[0099] According to this embodiment, the scale of the register 42 can bereduced. In addition, no contention occurs at all between the equalizer20 and the PLL in terms of phase characteristics in the coefficientcompensation process of the equalizer 20. The CCOMP 31 at this time cancompensate one coefficient by an average or mean correlation signalobtained by adding a plurality of data latched in the delay elements39A, so that the coefficient compensation can be performed withsufficient stability. The CCOMP 31 in this modified example has abouthalf as many as the coefficients to be compensated in the case where alltaps are asymmetric, and therefore the scale of its circuit can be abouthalf as large. Also, the circuit scale of the equalizer circuit 20itself can be about half as large because the number of the multipliers40A, which are the largest components, can be about half as many.

[0100] Note that the front-back symmetry Tas of the input waveform(solitary waveform) corresponding to a solitary magnetization in whichthis modification is effective is 7% or less, and if this is exceeded,even when the number of taps is increased, the equalizer circuit cannotexhibit its performance sufficiently, which results in a considerabledeterioration of the apparatus performance.

[0101] If the leading edge of the mesial-point width PW50 is designatedas T1 and the trailing edge is designated as T2, the font-back symmetryTas of a solitary waveform is defined as:

Tas=T1−T21/PW50

(PW50=T1+T2)

[0102]FIG. 10 shows yet another embodiment of the equalizer circuit 20.

[0103] In this embodiment, a seven-tap transversal type equalizercircuit 20 is used and arranged such that negative coefficients of theequalizer circuit 20 are set by using positive coefficients, that is, byinverting outputs of the delay elements 39A.

[0104] In the case of waveforms having their foot portion shaped in arelatively monotonous form like in reproduced waveforms of solitarymagnetizations in magnetic recording, when the transversal equalizercircuit equalizes such a waveform, the tap coefficients have their signsalternate in such a manner as minus, plus, minus, plus, and so on asthey move toward both sides if the sign of the coefficient at the centertap is positive.

[0105] According to this embodiment, it is possible to invert and outputdata at tap positions that can be estimated to be negative coefficientsand, as a result, the need for the signs for the coefficient bits of theequalizer circuit is obviated, and the circuit scale of the equalizercircuit can be reduced. In addition, the scale of the registers forsetting coefficients can be reduced. Obviously, the same results can beobtained if the signs of the coefficient values are inverted.

[0106] The constitution and the operation of the coefficientcompensation circuit (CCOMP) 31 in this embodiment will be described indetail with reference to FIG. 11.

[0107] The CCOMP 31 according to this embodiment includes a simplifieddetection circuit 43 for, after the input signal of the equalizercircuit 20 (ADC output) is (1+D)-processed by the (1+D) processingcircuit 21B, outputting only the plus and minus signs of the bits of thesignal; an adder 41B functioning as an error calculating circuit forcalculating an error signal e from the output signal of the (1+D)circuit and the output signal of the detection circuit 44 formed of acomparator; a group of delay elements 39B for delaying the output signalfrom the simplified detection circuit 43; a multiplier 40B functioningas a correlation value calculating circuit for calculating a correlationvalue between the output signal of the group of delay elements 39B andthe output signal e of the error calculating means; an adder 41Dfunctioning as a correlation value adding circuit for sequentiallyadding up, by using a delay element 39C, the output signals of themultiplier 40B; a coefficient compensating direction calculating circuit(DCAL) 48 for calculating a coefficient compensation amount according toa signal from the adder 41D, which is a sum of additions a fixed numberof times; a coefficient error compensation circuit (COUNTER) 49 formedof an up-down counter, for example, for compensating the coefficientvalue of the equalizer circuit by the output signal of the DCAL 48; acoefficient input/output selector (IOSEL) 50 formed of a switch tocontrol input and output of the coefficient values; and a tap numberswitch (TAPSW) 46.

[0108] The correlation value calculating circuit (adder) 41D accordingto this embodiment stops sequential additions of correlation values fora fixed period of time after coefficient compensation is carried out. Tobe more specific, in the adder 41D, additions are performed sequentiallyin step with the addition clock CLK 1 which occurs at the same rate asthe data periods or cycles. Added-up data is converted into an up/downsignal of the COUNTER 49 by DCAL 48. After additions are performed 32times in step with CLk 1, an up/down signal is received by COUNTER 49 instep with CLK 2, and the tap coefficient value, supplied to COUNTER 49by the action of IOSEL 50, is updated. The updated tap coefficient valueis reflected to the equalizer circuit 20 by the action of IOSEL 50 andin response to a gate signal SGT. At this moment, however, the (1+D)output signal to be supplied to the CCOMP 31 does not immediatelyreflect the just updated coefficient value, so after the elapse of afixed period of time (e.g., a total delay time of the equalizer circuit20 and the (1+D) processing circuit 21), a reset signal RS is sent tothe correlation value adder 41D to let the adder 41D discard theaddition information about a correlation value related to a tapcoefficient value not yet updated. By a setting value of the tap numbersetting register 47, the TAPSW 46 is controlled so as not to performcoefficient compensation at tap positions of coefficients K±3 of theseven-tap transversal type equalizer circuit 20 when the tap number 5 isset. In this case, the coefficients K±3 are always set at “0” and theoperation of the section related to coefficient compensationcorresponding to coefficients K±3 is stopped.

[0109] According to this embodiment, correlation data is not obtainedwhile coefficients are being compensated, but by providing a haltperiod, correlation data is accumulated invariably under a fixed tapcoefficient value. Therefore, no oscillatory errors occur attributableto the loop delay (delay by TREQ 20 and CCOMP 31) which tend to occurwhen CLMS (clipped least mean square) and LMS (least mean square)operations are performed which are conventional coefficient compensationalgorithms. The coefficient compensation circuit is essentially an openloop circuit, and therefore can perform signal processing steps such asaveraging (corresponding to the correlation value calculating means inthis embodiment) a sufficient number of times (32 times is specified inthis embodiment, but in fact any number of times is possible) withoutregard to the loop delay, thus holding great promises for higheraccuracy in coefficient compensation. Moreover, in this embodiment,because a plurality of tap coefficients are updated simultaneously, thetime to convergence is short. Though the time depends on the number ofadditions performed, the coefficients converge sufficiently by theamount of learning as long as about one sector (several thousand bits).

[0110] If the signal input to the equalizer circuit is received with arelatively high resolution and shows good symmetry, the number of tapsprovided can be reduced. According to this embodiment, signalequalization can be performed with desirable coefficients which do notgive rise to coefficient truncation errors compared with a case wherethe coefficients are obtained by seven-tap compensating the coefficientcompensation with only the coefficients at the two extreme ends set at“0”, are applied to the equalizer circuit. In addition, outputs at thegates where the tap coefficients are set at “0” are fixed and notswitched, the current consumed in those areas is reduced, so that thetotal power consumption of the circuit can be reduced.

[0111] In this embodiment, the input signal (ADC output) to theequalizer circuit 20 is subjected to a partial response process (1+Dprocess) 21 and then supplied to the coefficient compensation circuit(CCOMP) 31, but obviously this 1+D process need not be included in theCCOMP circuit as shown in FIG. 8. Output of the simple detection circuit(SDET) 43 is not restricted to sign bits, and may be data of severalbits.

[0112] The signal to noise ratio of the correlation signal can beimproved by calculating a compensation amount from a correlation signalbetween an error signal supplied by DET 44 and a signal obtained bysubjecting the input signal of the equalizer circuit 20 to a partialresponse waveform process and then to a simplified detection process(SDET 43). Consequently, the convergence of coefficient compensation isimproved, so the need for means for storing the data pattern isobviated.

[0113] According to this embodiment, coefficient compensation using arandom, arbitrary data pattern is possible, and coefficient compensationat the user site is also possible. Therefore, in such a case where thecharacteristics of the head and the recording medium change with time,if coefficient compensation is carried out when power is turned on, forexample, it is possible to maintain the optimum equalizer circuitcondition on the apparatus at all times. Because a data pattern which isnecessary for the coefficient compensation circuit to carry outcoefficient compensation is not specified, means to store a data patternneed not be mounted inside or outside the apparatus, so the circuitscale can be reduced.

[0114] In magnetic disk apparatuses, generally the combination of thedisk and the head remains unchanged, and therefore, it is often possiblefor the magnetic disk apparatus to maintain its sufficient performanceonly if coefficient compensation is carried out before the apparatus isshipped even if coefficient compensation is not carried out at the usersite. In this case, it is possible to erase the random data pattern(training area) for coefficient compensation on the magnetic disk, whichwas used when the coefficients were compensated, and ship the apparatus.This training area can be used as the storage area for user data, so theformat efficiency of the apparatus can be improved.

[0115] A modification of the coefficient compensation circuit (CCOMP) 31will be described with reference to FIG. 12.

[0116] In this embodiment, the coefficient compensation circuit includesa selection circuit (TAPSEL) 51 formed of switches to select the tapcoefficients to be compensated; a coefficient compensation amount(delta-value) calculation circuit for new coefficient (DELTACAL) 45described in detail with reference to FIG. 11; and coefficient temporaryholding circuit (COEFTEMPRSS) 52 formed of registers. The selectioncircuit (TAPSEL) 51 operates in an interlocked manner with thecoefficient temporary holding circuit 52, and when the compensation-amount for each tap coefficient value is calculated, the TAPSEL 51selects specified tap positions. The order of selection of the tappositions is from those closer to the center to remoter ones (the orderis basically not specified). When the coefficient values for those tapsare set in the coefficient temporary holding circuit by controlling theTAPSEL 51, all the tap coefficients are set in the coefficient registers42 by signal KS.

[0117] According to this embodiment, as described with reference to FIG.11, the coefficient compensation circuit 31 according to the presentinvention is essentially formed as an open loop. Therefore, if thelinearity and the randomness of the signal input to the equalizercircuit 20 are guaranteed, the respective tap coefficients need not becompensated by the same information (simultaneously). As shown in thisembodiment, the tap coefficients can be compensated in a time sharingmanner by using the selection circuit 51 and the coefficient temporaryholding circuit 52 and, as a result, the circuit scale can be reducedsubstantially.

[0118] Another embodiment of the coefficient compensation circuit(CCOMP) 31 will be described with reference to FIG. 13.

[0119] In this embodiment, the CCOMP 31 of the equalizer circuit 20receives the output signal of ADC 19 and operates in step with adecimated clock. Note that the output signal of ADC 19 is the inputsignal of the coefficient compensation circuit 31 of the equalizercircuit 20 which is formed by replacing the delay elements 39A withlatches 39A′. The decimation number in this embodiment is 1, and thefrequency of the decimation clock is ½ of the data clock frequency.There are two systems: one system where output of SDET 43 is firstlatched by a latch 39B′-1 in step with the data clock and thendecimated, and the other system where the output of SDET 43 is directlydecimated and latched by a latch 39B′-2. Reference numeral 39B′ denoteslatches by which input signals corresponding to the tap positions of theTREQ 20 can be obtained in step with the decimation clock.

[0120] As described above, the coefficient compensation circuitaccording to the present invention is only required to supply errorsignals between input and output signals of the equalizer circuit, whichcorrespond to the respective tap coefficient positions. Therefore, theerror signal between the input and output signals of the equalizercircuit need not necessarily be continuous but may be decimated asproposed in this embodiment.

[0121] According to this embodiment, by decimation, the operationfrequency of the coefficient circuit cane be reduced to 1/(decimationnumber+1), so that power consumption during a coefficient compensationoperation can be reduced substantially without increasing the scale ofthe circuit.

[0122] A modification of the means for obtaining the coefficients willbe described with reference to FIG. 14.

[0123] In this embodiment, the coefficient compensation of the equalizercircuit is carried out outside and the coefficient compensation circuit31 is not used.

[0124] In this embodiment, the equalizer circuit is provided with a dataholding circuit 53 formed of latches 39C′ for holding a signal input tothe transversal type equalizer circuit 20 (namely, output of ADC 19) fora data segment having a length twice or more longer than a total of tapsof the equalizer circuit in time with the data clock, and also aselection circuit (CLKSEL) 54 formed of a switch to output, to theoutside, data held in the data holding circuit 53 by switching from thedata clock to another clock (a read clock).

[0125] Beside the above-mentioned sequential compensation method, thereis another method for obtaining tap coefficients of the equalizercircuit 20. This method is to serially store a considerable amount ofthe input signal of the equalizer circuit, and give a sequence of idealoutput corresponding to the sequence of the input signals to therebyobtain coefficients of the generally known Wiener filter (a filter witha tap coefficient for minimizing the square error). By applying thisembodiment, it is possible to take out the held data and obtain anoptimum solution by using an external personal computer, a controllerCNT 6 in a magnetic disk apparatus and so on to perform a matrixoperation.

[0126] According to this embodiment, the data segment length of the dataholding circuit 53 can be reduced to about twice the number of taps ofthe equalizer circuit by making contrivance to the pattern or the like,so that the circuit scale can be made smaller than in a case of forminga coefficient compensation circuit. However, a longer data segmentationlength reduces the effects of noise, and obviously helps to obtainbetter tap coefficients.

[0127] With reference to FIG. 15, description will now be made of theerror detection circuit (ERRC) 32 instrumental in optimizing theparameters in this embodiment.

[0128] The ERRC circuit 32 includes a second detection circuit (DET2) 55formed of a comparator, for example, for receiving the same input signalas the input signal to the detection circuit (ML) 22, an adder 41serving as the error calculating circuit for calculating an error signalin the second detection circuit 55 from the input signal to and theoutput signal from the second detection circuit 55, a distinction ordecision circuit (DIST) 56 formed of a comparator, for example, foroutputting a count signal when an error signal is larger than a fixedthreshold value set in a register 57, and a counter 49 for countingcount signals.

[0129] The error signal between the input signal to the detectioncircuit (ML) in the signal processing circuit and the target amplitudeat the equalizer circuit is obtained by using the second detectioncircuit 55 and the error calculating circuit (adder 41). This errorsignal is compared with a fixed threshold value set in theabove-mentioned distinction circuit, and if the error signal is largerthan the threshold value, a distinction output is at the “1” level andif not, the distinction output goes to the “0” level. Theabove-mentioned counter increments only when output of the distinctioncircuit is “1”. In this embodiment, the DET2 is indicated as a detectorof every bit, but the ML22 shown in FIG. 1 may be used instead of theDET2.

[0130] The error signals in the error detection circuit are distributedon both the positive and negative sides with “0” as the center ofdistribution and in a substantially normal distribution. Therefore, theratio of the count value to a total population parameter is decided bythe variance value of the error signals and the threshold value of thedistinction circuit. In other words, if the total population parameter,a threshold value and a count value are decided, the variance value ofthe error signal can be obtained. Because generally the performance(BER) of the detection circuit in the apparatus is decided by thequality of signal (the variance value for example) input to thedetection circuit, the BER of the apparatus can be estimated by findingthe variance value.

[0131] When the parameters are to be optimized, if differences in thevariance values can be detected by varying the setting values of theparameters, this is enough. If the factors governing the apparatusperformance are sampled separately and the parameter values at which theerrors (variance value) are smallest are obtained, the parameters can beoptimized.

[0132] According to this embodiment, a necessary population parameter(number of samples) for achieving the accuracy of the ratio of the countvalue to a total population parameter of one to two percent is severalthousands, so that the amount of information as many as several hundredbytes (about one sector) is enough. Therefore, compared with theconventional method of optimization by measurement of BER, the requiredtime is about one-one hundred thousandth (1/100,000). For this reason,optimization of a larger number of parameters can be performed in arelatively short time, so that the performance of the apparatus isthereby expected to improve. It is expected that a reduction ofadjustment time contributes to a reduction of the apparatus cost.

[0133] If an output monitor or the like is added to the equalizercircuit, the error detection circuit can be installed external to theapparatus as a tool for adjusting the magnetic disk device.

[0134] In the embodiment mentioned above, the detection level in thecomparison in the detection circuit 55 has been described as fixed, buta variation of the present invention can be made such that the detectionlevel of the second detection circuit (DET2) 55 shown in FIG. 16 can beset arbitrarily in the detection level register 58.

[0135] If it is possible to arbitrarily set the detection level of thesecond detection circuit 55 in the error detection circuit, detectionwith a varying threshold value becomes possible, and then the followingadvantages can be offered. Normally, the second detection circuit 55 hasbinary detection levels of +0.5 and −0.5 to detect three values of +1, 0and −1. For example, if a data pattern which can take only two values of+1 and −1 as the output data pattern of the equalizer circuit is to bedetected, detection errors are likely to occur at the above-mentioneddetection level depending on the magnitude of error and noise.

[0136] According to this embodiment, if the threshold value (value setin the detection level register) is set close to “0”, the detectioncircuit can be operated as a substantially binary detector, so that thedetection performance improves (the antinoise performance improves twicehigher than before) and a more accurate value of error signal can beobtained. Therefore, more accurate optimization of the apparatus can beperformed.

[0137] As shown in FIG. 16, a plurality of detection levels can be setfor the second detection circuit (DET2) 55 by adding a register 59.

[0138] If the second detection circuit 55 can be operated as a detectioncircuit for binary output (+1, −1) with one threshold value (0), thedetection performance with data of a specific data pattern can beimproved (the antinoise performance can be improved twice higher). Inthis embodiment, the register 59 is used to set the number of detectionlevels (0, 1, 2) of the second detection circuit 55. When the number ofdetection levels is ‘2’ as set in the register 59, the DET2 operates asa detection circuit to supply ternary outputs (+1, 0, −1) with referenceto positive and negative threshold values obtained from a value set inthe register 58 (for example, threshold values are −0.5 and +0.5 if theregister 58 has a value of 0.5), when the number of detection levels is“1”, the DET2 operates to supply binary outputs (+1, −1) with referenceto a threshold value of 0 regardless of the register 58, and when thedetection level is “0”, the DET2 operates to output “0”.

[0139] According to this embodiment, the detection level can be setarbitrarily only by the register 58. By using the registers 58 and 59,the error signal can be obtained with higher accuracy. When thedetection level is set at “0”, the input signal to the LML 22 can beinput directly to the distinction circuit.

[0140] Description will next be made of optimization of the writecurrent value by using the error detection circuit 32 according to theembodiment of the present invention.

[0141] In optimization of the write current using this embodiment, awrite current setting register, a write current setting circuit (IWC)60, and a write current output terminal of the signal processing circuit38 are used.

[0142] The relation between the write current value of the recordinghead 9 of the magnetic disk drive 7 and the reproduced output amplitudeinput to the signal processing circuit 38 is substantially as shown inFIG. 5. Generally, the larger the reproduced output amplitude detectedby the reproducing head 8, the better the quality of the reproducedsignal becomes. If, for example, repetitive data, which oscillates insuch a signal pattern as . . . +1, +1, −1, −1, +1, +1 . . . when thisdata is input to the detection means (ML) of the signal, is recorded,the typical signal amplitude is controlled by the automatic gain controlcircuit (AGC) such that the amplitude fluctuates only at two levels ofpositive and negative equalization target values, so that there is no“0” level. The smaller the reproduced output amplitude is, the largerthe ratio of noise to signal becomes, so the error signals occur moreoften, and also the variance of the signals input to the distinctionmeans of the ERRC is greater as shown in FIG. 5.

[0143] Therefore, by judging an error signal by a suitable negativethreshold value in the distinction means of the error detection circuit32 so that the occasions when the error signal is larger than thethreshold value are counted each time the write current value ischanged, the write current at which the count value (number of counts)is greatest (namely, the signal to noise ratio is greatest) can bedetected. Note that in reproduction of recorded signals having thespecific data pattern, the signals have only a substantially singlefrequency component and for which reason, the signal reproduction is notmuch affected by errors of the equalizer circuit or the like, errors ofthe write precompensation circuit, and the nonlinearity of thereproducing head and therefore optimization of the write current withhigh accuracy can be achieved. If results of several measurements, whichwere carried out with various threshold values in the distinction meansare used, the deterioration of accuracy due to DC offset, for example,can be avoided, and obviously an improved equalization performance canbe realized.

[0144] Description will then be made of optimization of the sensecurrent using the error detection circuit 32 according to the embodimentof the present invention.

[0145] In optimization of the sense current using this embodiment, thesignal processing circuit 38 includes a reproducing head (8) sensecurrent setting register, a sense current (Is) setting circuit ISC 61and a sense current output terminal.

[0146] When a magnetoresistive effect element is used to form areproducing head 8 of a magnetic disk apparatus 7, if bias magnetizationof the head 8 is not optimized, the amplitude of the reproduced waveformvaries due to different polarities of solitary magnetizations. Thewaveforms of solitary waves are input to the signal processing circuit38 through AC coupling, the input signal to the detection circuit shiftswith respect to the 0 level, as shown in FIG. 6. Therefore, data isrecorded in a recording pattern such that the magnetization density onthe recording medium is lowest, and errors are detected by ERRC 32,described below, each time the sense current is changed.

[0147] The detection level of output of the second detection circuit 55is set at “0” so that the input signal supplied to the detection circuitis supplied to the distinction circuit, and the threshold value of thedistinction circuit is set at “0” so that each time the sense currentvalue is changed, the occasions that the threshold value “0” is exceededfor a fixed period of time are counted. When the bias magnetization bythe sense current is not optimized and the amplitude ratio varies, themean value of the error signals shifts from “0”, so that the ratio ofthe count value to a total population parameter shifts from ½. Note thatwhen the input signal to the detection circuit 22 has been quantized,the above-mentioned ratio of the count value shifts rather greatly atthe set optimum sense current, so obviously it is necessary to considerthe number of bits in quantization.

[0148] According to this embodiment, by selecting a sense current valueat which the shift of the mean value of error signals from “0” issmaller than the reference value and the variance of error signals issmallest, the optimum sense current can be obtained. At this time, thecoefficient values of the equalizer circuit and the writepre-compensation amount need not be optimum ones.

[0149] Description will be made of optimization of the DC offsetcompensation amount of ADC 19 using the error detection circuit 32according to the embodiment of the present invention.

[0150] In optimization of the DC offset compensation amount of ADC usingthis embodiment, an offset setting circuit 62 for DC offset compensationand an offset compensation register are used in ADC 19, and the offsetamount when no signal is supplied is detected by the error detectioncircuit 32.

[0151] By making arrangement such that the input signal to the detectioncircuit 22 is comprised only of a substantially random and small circuitnoise, and detecting errors by the error detection circuit 32 each timethe offset compensation amount is changed, the offset compensationamount at which the shift of the mean value of the error signals from“0” is smallest is taken as the optimum offset compensation amount. Itis obviously appropriate to include the offset setting circuit 62 in theinput portion of the ML 22 when the equalizer circuit 20 and thedetection circuit 22 (ML) are analog circuits.

[0152] According to this embodiment, the offset of the circuit portioncan be adjusted relatively easily. It should be noted that thecoefficient values of the equalizer circuit may be basically arbitraryvalues.

[0153] As another modification, any other method of offset detectionthan mentioned above may be used.

[0154] In optimization of the DC offset compensation amount of ADC 19using this embodiment, the signal processing circuit 38 includes anoffset setting circuit 62 for DC offset compensation and an offsetcompensation register, and the error detection circuit 32 is used bysupplying an input signal of a single frequency.

[0155] Write data is specified as having a single recording frequency,and the same error detection is used as the one described when referencewas made to the optimization of the write current value in theembodiment described above. When an offset occurs, the AGC or PLL'soperates to compensate the input signal of the detection circuit so asto comply with the equalizing target value, but the AGC and the PLLbasically do not have a function to compensate the offset; therefore, asa result of the control operation, jitter (noise) increases or a shiftfrom the equalizing target value occurs. Therefore, by detecting errorseach time the set offset compensation value is changed, the offsetcompensation amount is searched at which the variance of errors of inputto the detection circuit 22 is smallest, and the offset compensationamount at this time is taken as the optimum offset compensation amount.

[0156] According to this embodiment, the same means as in theoptimization of the write current value mentioned above can be used.Therefore, prior to optimization of the write current, the offsetadjustment described in this embodiment can be executed, and the time ofadjustment can be shortened. Note that the coefficients of the equalizercircuit, the write pre-compensation amount, the write current value andthe sense current may basically be arbitrary ones.

[0157] Description will next be made of optimization of the tapcoefficients of the equalizer circuit 20 using the error detectioncircuit 32 according to the present invention.

[0158] In optimization of the tap coefficient values of the equalizercircuit 20 using this embodiment, a coefficient value register to givecertain characteristics to the equalizer circuit and an error detectioncircuit 32 are used, but the coefficient compensation circuit 31 is notused. When coefficient compensation using the coefficient compensationcircuit 31 is executed in a specific recording/reproducing area, it issometimes possible to roughly estimate the coefficient values in othernearby areas. In this case, error detection is performed with estimatedcoefficient values set in the coefficient value registers, and adecision is made whether or not to adopt the coefficient valuesestimated from the error values.

[0159] At this time, the write data is random data and the detectionlevel of the second detection circuit 55 is set at “2”.

[0160] According to this embodiment, also in ordinary reproduction ofuser data, by setting coefficient values in the coefficient register andchecking the error amount by the error detection circuit 32, whether thecoefficient values are adequate or not can be decided. Moreover, it ispossible to prepare a couple of combinations of coefficient values, andselect a combination of coefficient values by which the variance ofequalization errors is smallest.

[0161] Description will be made of optimization of the writepre-compensation amount using the error detection circuit 32 accordingto the embodiment of the present invention.

[0162] In optimizing the write pre-compensation amount using thisembodiment, a compensation value register of the write pre-compensationcircuit (WPC) 12 is used to compensate the flux reversal positions inrecording data according to a data sequence. As the recording densitybecomes higher and the bit intervals become closer, the flux reversalpositions become closer. Therefore, data is written while the writepre-compensation circuit 12 estimates the rate of movement ofmagnetization and compensates the reversal positions of magnetization.In this process, the error detection circuit decides whether or not thecompensation could be achieved accurately.

[0163] In this process, data to be recorded is random data, and data isrecorded using different values of the compensation value register 12,and error detection is performed each time the recorded data isreproduced. The write pre-compensation amount can be optimized byselecting a write pre-compensation amount at which the variance oferrors input to the detection circuit is smallest.

[0164] Another modification of the error detection circuit 32 describedabove will be described with reference to FIG. 17.

[0165] In this embodiment, the error detection circuit 32 includes adistinction circuit 56 to receive an input signal which is also suppliedto the detection circuit 22 and output a count signal when the inputsignal is larger than the threshold value, a counter 49 to count countsignals output from the distinction circuit 56, and a register 57 to setthe threshold value.

[0166] According to this embodiment, by arranging such that the inputsignal to the detection circuit comprises only a substantially randomcircuit noise and detecting errors each time the offset compensationamount setting is changed, and thus selecting an offset compensationamount at which the shift of the mean value of error signals output fromthe equalizer circuit from “0” is smallest, the offset compensationamount can be optimized. Likewise, the sense current of themagnetoresistive element type reproducing head can be optimized.

[0167] Yet another modification of the error detection circuit 32, shownin FIG. 17, according to the present invention will be described withreference to FIG. 18.

[0168] The error detection circuit 32 includes a first distinctioncircuit 56 to receive an input signal which is also sent to thedetection circuit 22 and output a count signal when an input signal isless than the threshold value, a first counter 49 to count count signalsof the first distinction circuit 56, a second distinction circuit 56′ tooutput a count signal when an input signal is larger than the thresholdvalue, a second counter 49′ to count count signals output from thesecond distinction circuit 56′, an adder 41 to subtract the count valueof the second counter 49′ from the count value of the first countermeans 49, a register 63 to hold the subtraction result, and a register57 to set the above-mentioned threshold value.

[0169] According to this embodiment, by using the output signal of theequalizer circuit directly in the error counting process, it is possibleto optimize offset compensation and also optimize the sense current ofthe magnetoresistive effect type reproduction head.

[0170] A still further modification of the error detection circuit 32shown in FIG. 17 will be described with reference to FIG. 19.

[0171] In this embodiment, by using the error detection circuit 32 shownin the embodiment in FIG. 17 or 18, of the whole input signal to thedetection circuit 22, the remaining signal from which the sign bits (SB)have been removed is used as the input signal.

[0172] When the sign bits are removed from the input signal to thedetection circuit (output from the equalizer circuit), if the originalsignal is negative, the signal is converted into a positive signal, andif the original signal is positive, the signal remains unchanged (oncondition that the original signal is expressed in 2s complements). Ifthe output signal of the equalizer circuit has a substantially singlefrequency component of . . . +1, +1, −1, −1, +1, +1, −1, −1, . . . thesignal from which sign bits have been removed is converted as shown inFIG. 7.

[0173] According to this embodiment, if the threshold value of thedistinction circuit is set in the neighborhood of the equalizationtarget value of the equalizer circuit, the variance of errors from thetarget value can be detected.

[0174] An additional modification of the error detection circuit 32,shown in FIG. 17, according to the present invention will be describedwith reference to FIG. 20.

[0175] In this embodiment, another error detection circuit other thanthose described above is used. To be more specific, an error detectioncircuits 32 shown in FIG. 18 or 19 and another error detection circuitin FIG. 20 are used. In this embodiment, there are two modes: a firstmode is that, of the whole input signal to the detection circuit 22, thesignal from which the sign bits (SB) have been removed is used as theinput signal and a second mode is that the sign bits (SB) are includedin the input signal. The mode is switched by applying the output of aregister 64 to an AND gate 65.

[0176] The circuit according to this embodiment is simpler than thesecond detection circuit DET in ERRC, and offset control, write currentoptimization and sense current optimization can be performed by asubstantially same method.

[0177] A circuit for resetting PRE-CODER 13 according to the presentinvention will next be described.

[0178] In this embodiment, in order to improve the reliability ofrecording and reproduction of a specific recorded data pattern requiredto optimize the parameters, there is provided a circuit to resetPRE-CODER 13 just before a “sync bite” to indicate the start of datawhen recording data.

[0179] According to this embodiment, the magnetized condition of thedata pattern from the sync byte on can be defined, and it is possible torecord a specific pattern required to optimize the parameters. Also, aspecific pattern to be recorded when checking the magnetic disk drive 7before its shipment can be recorded while the magnetized condition isdefined, which raises hopes for improvement in reliability of the drive.

[0180] A sync byte code sequence in the present invention will bedescribed with reference to FIGS. 21 and 22.

[0181] In this embodiment, to improve the reliability of recording andreproduction of a specific data pattern required to optimize theparameters, a code sequence corresponding to the sync byte according tothe present invention is applied in the sync byte detection circuit 25.The code sequence corresponding to the sync byte is set in a register68, and in a logic element SOR 66, the code sequence is compared with acode sequence of ML output stored in delay elements (DLY) 39D, and alloutput bits are processed by a logic element NOR circuit 67 to form adetection signal of the sync byte, and the detection result is outputthrough SPIF 33 to HDC 4. As shown in FIG. 22, by using a recordingsystem such that a flux reversal occurs at data “1” and the writecurrent direction is maintained at data “0”, the sync byte is formed bya code sequence such that the start of serial data begins with “0” andno continuation of data “1” exists in a sequence of serial data. Inaddition to the above-mentioned embodiment, the code sequence of thesync byte is arranged such that a sequence of codes “0” and “1” in MLoutput corresponding to a sync byte differs for more than ½ of a datasequence of the sync byte from a sequence of codes “0” and “1” in MLoutput corresponding to a preceding byte recorded continuously beforethe sync byte. Note here that the code sequence (NRZI) is “001000100”,and “001100110” is set in the register 68 corresponding to ML output.

[0182] According to this embodiment, it is possible to form a sync bytewhich does not interfere with the data pattern of a preceding byte,written before, for the AGC and the PLL, recorded before and which ishardly susceptable to nonlinear distortion in recording. Therefore, async bytes can be detected relatively easily even if the write current,the sense current and the coefficients of the equalizer circuit are notoptimized.

[0183] In another embodiment of the present invention, for the ACC 29,target amplitude value setting means is used by which the targetamplitude value of the automatic gain control circuit (AGC) can bevaried by using the setting values in a register as shown in FIG. 1.

[0184] According to this embodiment, when the resolution of input signalis low, by using a small target amplitude value of AGC, the signal canbe prevented from being saturated at various portions of the signalprocessing circuit, and for example, the effect of impulse noise can bereduced. When the resolution of input signal is high, conversely, byusing a large target amplitude value of AGC, the ratio of noise, such asquantization noise in ADC 19 and circuit noise in VGA 17 and LPF 18relative to the signal can be reduced, by which the apparatusperformance (BER, for example) can be improved.

[0185] Another embodiment of the present invention will be describedwith reference to FIG. 23.

[0186] This embodiment is a case in which the present invention isapplied to the magnetic disk drive in the form of a two-chip signalprocessing LSI.

[0187] Generally, the signal processing circuit realized in a one-chipLSI including all signal processing elements is preferable, but whenpower consumption is large, it is more preferable to form the circuit intwo or more subdivided chips.

[0188] In order to solve this problem, in this embodiment, the signalprocessing circuit is formed in a LSI with two chips, an analog chip38-A and a digital chip 38-D, and the outputs of the automatic gaincontrol circuit (AGC) and the automatic phase lock loop (PLL) on thedigital chip are supplied through current-output type VDAC 30 and PDAC27 via pin terminals to a variable gain amplifier (VGA) 17 and a voltagecontrolled oscillator (RVCO) 28 on the analog chip 38-A. The otherdevices mounted on the analog chip 38-A include VGA 17, LPF 18, ADC 19,RVCO 28, WVCO 16, a servo signal processing circuit made up of a peakhold circuit (P/H) 69 and a comparator (CMP) 70 for servo signals ofGray code, and a register interface for the analog chip (ARGIF) 72.Further, the devices mounted on the digital chip 38-D include an addressmark finder circuit (AMF) 73 for detecting an address mark from theoutput pulse train of CMP 70.

[0189] According to this embodiment, the signals are output in the formof DAC current from the digital chip, so that the effects of noiselikely to enter the signals from the digital chip can be reduced, andthe required number of pins can be substantially reduced compared with acase where those signals are output in several-bit codes. The ADC, RVCOand WVCO which require analog circuit design method and layout methodare preferably arranged on the analog chip from viewpoints ofperformance, circuit scale, and power consumption. Needless to say, theabove-mentioned circuits can be arranged on the digital chip and, inthis case, the number of signal pins between the analog and digitalchips can be further reduced.

[0190] In this embodiment, the signal interface between the signalprocessing LSI and the other circuit portion of the magnetic disk drivehas the following features.

[0191] First, the analog, reproduced signal from the R/W IC, writecurrent and sense current setting signals and P/H output signal aretransmitted to and from the analog LSI. Second, signals in digital formare transmitted to and from the HDC and the CNT. Third, the signalstransmitted between the analog and digital LSI's are the digital outputfrom the ADC and DAC current signals from the PDAC used as controlsignals of the RVCO and the VGA.

[0192] When the signal processing circuit is formed in a two-chipstructure, the process design method and the manufacturing method can beselected separately for the respective chips, so that the performanceand the efficiency of development of the respective chips can beexpected to improve. For example, the analog chip can be manufactured bythe bipolar and BiCOMOS LSI processes which have shown favorable analogcharacteristics and a history of proven success. Needless to say, it ispossible to manufacture the two chips by the same BiCMOS or CMOSprocess. A possible method in design and manufacture is to apply theoptimum manual layout for the analog portion on one hand and use themost suitable automatic layout for the digital portion on the otherhand. Moreover, less expensive packages can be produced by subdivisionsof power consumption, production yield can be improved by use ofsmall-size chips, and consequently cost reduction in LSI chips can berealized. In addition, when such an LSI is used, a cost reduction of themagnetic disk drive can be achieved. In the embodiments mentioned above,an example of a two-chip structure has been shown, but the presentinvention is not limited to this structure and a structure of threechips or a further subdivision is possible.

[0193] The present invention is not limited to Viterbi decoding or PR4,but any other known amplitude discrimination method may be used. Acombination of the partial response waveform process such as EPR andEERP and Viterbi decoding or a combination with Trellis codingmodulation method can be applied.

[0194] If the coefficient compensation circuit and the error detectioncircuit of the equalizer circuit according to the present invention isapplied to a signal processing circuit or a magneticrecording/reproducing apparatus adapted to high-speed signaltransmission, the optimization of the parameters of the circuit and theapparatus can be achieved relatively easily and in a short time.Accordingly, the signal processing circuit or the magneticrecording/reproducing apparatus will have better performance as a matterof course, the adjustment time can be shortened, and a substantial costreduction of the circuit and the apparatus can be expected.

1. A signal processing circuit comprising: an equalizer circuit; acoefficient compensation circuit having an input connected to saidequalizer circuit, for sequentially compensating tap coefficient valuesof said equalizer circuit; and a phase detection circuit, connected toreceive an output signal of said equalizer circuit, for sequentiallydetecting a phase of a signal input to said equalizer circuit, whereinsaid equalizer circuit includes a transversal type equalizer circuitwith five or more taps, and wherein, of tap coefficients of saidequalizer circuit, the tap coefficients adjacent on both sides to acenter tap are the same value.
 2. A signal processing circuit accordingto claim 1, wherein arrangement is made such that negative coefficientvalues of said transversal type equalizer circuit are set by positivecoefficient values by inverting either output values or coefficientvalues of tap delay means.
 3. A signal processing circuit according toclaim 1, wherein the input signal of said equalizer circuit ispartial-response-waveform processed and input to said coefficientcompensation circuit.
 4. A signal processing circuit according to claim1, wherein said coefficient compensation circuit includes firstdetection means for detecting said input signal of said equalizercircuit; second detection circuit for detecting said output signal ofsaid equalizer circuit; error calculating means for calculating an errorsignal from said output signal of said equalizer circuit and a signal ofsaid second detection means; delay means for delaying the output signalof said first detection means; correlation value calculating means forcalculating a correlation value between the output signal of said delaymeans and the output signal of said error calculating means; correlationvalue adding means for sequentially adding output signals of saidcorrelation value calculating means; coefficient compensation amountcalculating means for calculating a coefficient compensation amount froma signal obtained by adding output signals of said correlation valueadding means a fixed number of times; and coefficient error compensationmeans for compensating a coefficient value of said equalizer circuit byan output signal of said coefficient compensation amount calculatingmeans, wherein the sequential addition of correlation values is stoppedfor more than a delay time after the coefficient compensation has beendone in said coefficient compensation circuit.
 5. A signal processingcircuit according to claim 4, wherein said coefficient compensationcircuit further includes delay time control means for controlling adelay time of said delay means; selection means for selecting a tapcoefficient to compensate in time with said delay length control means;and coefficient temporary holding means for temporarily holding a tapcoefficient compensated by said coefficient error compensation means,wherein said delay time is fixed when tap coefficient compensationamounts are calculated, and when tap coefficient values have beendecided by controlling said selection means, all tap coefficients arecompensated.
 6. A signal processing circuit according to claim 5,wherein the input signal of said equalizer circuit which is concurrentlysupplied to the equalizer circuit and the output signal of saidequalizer circuit are decimated and input to said coefficientcompensation circuit and said coefficient compensation circuit isoperated at a decimated signal frequency.
 7. A signal processing circuitaccording to claim 1, wherein, of the tap coefficients of thetransversal type equalizer circuit, the tap coefficients at positionssymmetric with respect to the center tap are the same value.
 8. A signalprocessing circuit according to claim 7, wherein arrangement is madesuch that negative coefficient values of said transversal type equalizercircuit be set by inverting either output values or coefficient valuesof tap delay means.
 9. An equalizer coefficient optimizing method foruse in an information recording/reproducing apparatus including anequalizer circuit of transversal type with five or more taps in which,of tap coefficients of said equalizer circuit, tap coefficients adjacenton both sides to a center tap are the same value, a coefficientcompensation circuit for sequentially compensating coefficient values ofsaid equalizer circuit, and a phase detection circuit for sequentiallydetecting phases of output signals of said equalizer circuit, the methodof optimizing the coefficients of said equalizer circuit comprising thesteps of: inputting reproduced waveforms of random, arbitrary datapatterns to said signal processing circuit; operating said coefficientcompensation circuit; reading tap coefficients which have beencompensated from said signal processing circuit; and storing said tapcoefficients in a non-volatile storage area in said informationrecording/reproducing apparatus.
 10. An equalizer coefficient optimizingmethod for use in an information recording/reproducing apparatusincluding an equalizer circuit of a transversal type with five or moretaps in which, of tap coefficients of said equalizer circuit, tapcoefficients at positions symmetric with respect to a center tap are asame value, a coefficient compensation circuit for sequentiallycompensating coefficient values of said equalizer circuit, and a phasedetection circuit for sequentially detecting phases of an output signalof said equalizer circuit, the method of optimizing the coefficients ofsaid equalizer circuit, comprising the steps of: inputting reproducedwaveforms of a random, arbitrary data pattern to said signal processingcircuit; operating said coefficient compensation circuit; reading tapcoefficients which have been compensated from said signal processingcircuit; and storing said tap coefficients in a non-volatile storagearea in said information recording/reproducing apparatus.
 11. Anequalizer coefficient optimizing method for use in an informationrecording/reproducing apparatus having a signal processing circuit,including an equalizer circuit, a coefficient compensation circuit forsequentially compensating coefficient values of said equalizer circuit,and a phase detection circuit for sequentially detecting phases of theoutput signal of said equalizer circuit, the method of optimizingcoefficients of said equalizer circuit, comprising the steps of:inputting reproduced waveforms of a random, arbitrary data pattern tosaid signal processing circuit; operating said coefficient compensationcircuit; reading tap coefficients which have been compensated from saidsignal processing circuit; and storing said compensated tap coefficientsin a non-volatile storage area in said information recording/reproducingapparatus.
 12. A method of optimizing coefficients in an equalizercircuit according to claim 11, wherein said equalizer circuit is atransversal type equalizer circuit with five or more taps, and of tapcoefficients of said equalizer circuit, tap coefficients adjacent onboth sides to the center tap are a same value.
 13. A method ofoptimizing tap coefficients of an equalizer circuit according to claim11, wherein said equalizer circuit is a transversal type equalizercircuit with five or more taps, and of tap coefficients of saidequalizer circuit, tap coefficients at positions symmetric with respectto a center tap are a same value.
 14. A signal processing circuitcomprising: an equalizer circuit; a coefficient compensation circuit,connected to an output of said equalizer circuit, for sequentiallycompensating tap coefficient values of said equalizer circuit; a phasedetection circuit, connected to an output of said equalizer circuit, forsequentially detecting phases of the signal input to said equalizercircuit; and a register for setting the number of taps, wherein saidregister is arranged to put the coefficient value at “0” at a specifictap position of said equalizer circuit according to contents set in saidregister, and said signal processing circuit stops the operation of thatportion of said coefficient compensation circuit which is related tosaid tap position.
 15. An information recording/reproducing apparatus,comprising: a head disk assembly; a signal processing circuit, connectedto said head disk assembly, and including an equalizer circuit, acoefficient compensation circuit for sequentially compensatingcoefficients of said equalizer circuit and a phase detection circuit forsequentially detecting phases of an output signal of said equalizercircuit; and a training area for coefficient compensation, recorded on arecording medium of said information recording/reproducing apparatus,wherein said training area is erased after a coefficient compensationoperation is performed, and is defined as an area for recording andreproducing user data.
 16. An information recording/reproducingapparatus according to claim 15, wherein said equalizer circuit is atransversal type equalizer circuit with five or more taps, and of tapcoefficients of said equalizer circuit, at least tap coefficientsadjacent on both sides to a center tap, and wherein arrangement is madesuch that negative coefficient values of said equalizer circuit be setby positive coefficient values by inverting either output values orcoefficient values of tap delay means.
 17. An informationrecording/reproducing apparatus according to claim 15, wherein, of thetap coefficients of said equalizer circuit, tap coefficients atpositions symmetric with respect to the center tap are a same value. 18.A signal processing circuit comprising: an equalizer circuit; a phasedetection circuit, connected to an output terminal of said equalizercircuit, for sequentially detecting phases of an output signal of saidequalizer circuit; data holding means for holding a signal input to saidequalizer circuit at timing of data clock for a length of a data segmenttwice or longer than a total number of taps of said equalizer circuit;and clock means for generating a clock signal to output data held insaid data holding means, wherein said clock signal is different from thedata clock.
 19. An information recording/reproducing apparatuscomprising: a head disk assembly; a signal processing circuit connectedto said head disk assembly and including an equalizer circuit, a phasedetection circuit, connected to an output of said equalizer circuit, forsequentially detecting phases of an output signal of said equalizercircuit, data holding means for holding a signal input to said equalizercircuit for a length of a data segment twice or longer than a totalnumber of taps of said equalizer circuit at data clock periods, andclock means for generating a clock signal to output data held in saiddata holding means, wherein said clock signal is different from saiddata clock; storage means, provided independently of said signalprocessing circuit, for storing said held data output from said signalprocessing circuit; means for calculating tap coefficient values of saidequalizer circuit based on data stored in said storage means; andnon-volatile storage means for storing said tap coefficient valuescalculated.
 20. An equalizer coefficient optimizing method for use in aninformation recording/reproducing apparatus having a signal processingcircuit including an equalizer circuit, a phase detection circuit forsequentially detecting phases of an output signal of said equalizercircuit, data holding means for holding a signal input to said equalizercircuit for a length of in a data segment twice or longer than a totalnumber of taps of said equalizer circuit at data clock periods, whereindata held in said data holding means is output at a clock signaldifferent from a data clock, the method of optimizing coefficients ofsaid equalizer circuit, comprising the steps of: storing said held dataoutput from said signal processing circuit in storage means providedindependently of said signal processing circuit; calculating tapcoefficient values of said equalizer circuit based on data stored insaid storage means; and storing said coefficient values in non-volatilestorage means.
 21. A signal processing circuit comprising: an equalizercircuit; an amplitude detection circuit, connected to an output of saidequalizer circuit, for sequentially detecting amplitudes of an outputsignal of said equalizer circuit; detection means for receiving, as aninput signal, said output signal from said equalizer circuit anddetecting said output signal; error calculating means for calculating anerror signal representing an amplitude error occurring at said detectionmeans from said input signal and an output signal of said detectionmeans; distinction means, having a threshold value set therein, foroutputting a count signal when an error signal is larger than thethreshold value; and counting means for counting said count signals. 22.A signal processing circuit according to claim 21, further comprising aregister for setting a detection level of said detection means.
 23. Asignal processing circuit according to claim 22, further comprising aregister for setting a number of detection levels of said detectionmeans.
 24. A signal processing circuit according to claim 22, furthercomprising target amplitude value setting means including a register forvariably setting a target amplitude value of said amplitude detectioncircuit.
 25. An information recording/reproducing apparatus comprising:a recording head; a signal processing circuit connected operatively tosaid recording head, said signal processing circuit including anequalizer circuit, an amplitude detection circuit, connected to anoutput of said equalizer circuit, for sequentially detecting amplitudesof an output signal of said equalizer circuit, detection means forreceiving said output signal as an input signal thereto and detectingsaid output signal, an error calculating means for calculating an errorsignal relating to an amplitude error occurring at said detection meansfrom said input signal and an output signal from said detection means,distinction means, having a threshold value set therein, for outputtinga count signal when an error signal is larger than said threshold value,counting means for counting said count signals, a register for setting adetection level of said detection means, and a register for setting anumber of detection levels of said detection means; and a write currentsetting register and a write current output terminal of said recordinghead, wherein recorded data is so formed as to have a single recordingfrequency, the number of detection levels of said detection means is setat “1”, each time the write current is changed, count values of saidcounting means are stored, a write current at which an errordistribution is smallest is calculated from said count values, and thewrite current value of said recording head is taken as the optimum writecurrent.
 26. An information recording/reproducing apparatus comprising:a recording head; a signal processing circuit connected operatively tosaid recording head, said signal processing circuit including anequalizer circuit, an amplitude detection circuit, connected to anoutput of said equalizer circuit, for sequentially detecting amplitudesof an output signal of said equalizer circuit, detection means forreceiving said output signal as an input signal thereto and detectingsaid output signal, an error calculating means for calculating an errorsignal relating to an amplitude error occurring at said detection meansfrom said input signal and an output signal from said detection means,distinction means, having a threshold value set therein, for outputtinga count signal when an error signal is larger than said threshold value,counting means for counting said count signals, a register for setting adetection level of said detection means, and a register for setting anumber of detection levels of said detection means; and a sense currentsetting register and a sense current output terminal of said recordinghead, wherein recorded data is recorded such that the magnetizationreversal density is smallest, and an output of said detection means isfixed at “0” at all times, and each time a sense current is changed,count values of said counting means, obtained using one or morethreshold values in said distinction circuit, are stored, and from saidcount values, a sense current at which an error distribution is smallestis calculated, and the sense current value of said recording head istaken as the optimum sense current.
 27. An informationrecording/reproducing apparatus comprising: recording and reproducingheads; and a signal processing circuit operatively connected to saidrecording and reproducing heads, said signal processing circuitincluding an equalizer circuit, an amplitude detection circuit,connected to an output of said equalizer circuit, for sequentiallydetecting amplitudes of an output signal of said equalizer circuit,detection means for receiving said output signal as an input signalthereto and detecting said output signal, an error calculating means forcalculating an error signal relating to an amplitude error occurring atsaid detection means from said input signal and an output signal fromsaid detection means, distinction means, having a threshold value settherein, for outputting a count signal when an error signal is largerthan said threshold value, counting means for counting said countsignals, a register for setting a detection level of said detectionmeans, and a register for setting a number of detection levels of saiddetection means; offset setting means for d.c. offset compensation; anoffset compensation register; and counting means for counting countsignals generated with reference to one or more threshold values of saiddistinction means, wherein input to said signal processing circuit isnot supplied, output of said detection means is put at “0” at all times,and each time the offset compensation amount setting is changed, thecount value is stored, and from said count values, the optimum offsetcompensation amount is calculated.
 28. An informationrecording/reproducing apparatus comprising: recording and reproducingheads; and a signal processing circuit operatively connected to saidrecording and reproducing heads, said signal processing circuitincluding an equalizer circuit, an amplitude detection circuit,connected to an output of said equalizer circuit, for sequentiallydetecting amplitudes of an output signal of said equalizer circuit,detection means for receiving said output signal as an input signalthereto and detecting said output signal, an error calculating means forcalculating an error signal relating to an amplitude error occurring atsaid detection means from said input signal and an output signal fromsaid detection means, distinction means, having a threshold value settherein, for outputting a count signal when an error signal is largerthan said threshold value, counting means for counting said countsignals, a register for setting a detection level of said detectionmeans, and a register for setting a number of detection levels of saiddetection means; offset setting means for d.c. offset compensation; andan offset compensation register, wherein input to said signal processingcircuit is so formed as to have a single frequency, the number ofdetection levels of said detection means is “1”, and each time theoffset compensation amount is changed, said count value of said countingmeans, obtained using one or more threshold values in said distinctioncircuit, is stored, and from the count values, the optimum offsetcompensation amount is calculated.
 29. An informationrecording/reproducing apparatus comprising: recording and reproducingheads; and a signal processing circuit operatively connected to saidrecording and reproducing heads, said signal processing circuitincluding an equalizer circuit, an amplitude detection circuit,connected to an output of said equalizer circuit, for sequentiallydetecting amplitudes of an output signal of said equalizer circuit,detection means for receiving said output signal as an input signalthereto and detecting said output signal, an error calculating means forcalculating an error signal relating to an amplitude error occurring atsaid detection means from said input signal and an output signal fromsaid detection means, distinction means, having a threshold value settherein, for outputting a count signal when an error signal is largerthan said threshold value, counting means for counting said countsignals, a register for setting a detection level of said detectionmeans, and a register for setting a number of detection levels of saiddetection means; and a register of coefficient values to give certaincharacteristics to said equalizer circuit, wherein recorded data israndom data, the number of detection levels of said detection means isput at “2”, and each time a coefficient value setting is changed, saidcount value of said counting means, obtained using one or more thresholdvalues of said distinction circuit, is stored, and from said countvalues, a coefficient value at which an error distribution is smallestis calculated, and this coefficient value is taken as the optimumcoefficient value.
 30. An information recording/reproducing apparatuscomprising: recording and reproducing heads; and a signal processingcircuit operatively connected to said recording and reproducing heads,said signal processing circuit including an equalizer circuit, anamplitude detection circuit, connected to an output of said equalizercircuit, for sequentially detecting amplitudes of an output signal ofsaid equalizer circuit, detection means for receiving said output signalas an input signal thereto and detecting said output signal, an errorcalculating means for calculating an error signal relating to anamplitude error occurring at said detection means from said input signaland an output signal from said detection means, distinction means,having a threshold value set therein, for outputting a count signal whenan error signal is larger than said threshold value, counting means forcounting said count signals, a register for setting a detection level ofsaid detection means, and a register for setting a number of detectionlevels of said detection means; record compensation means forcompensating magnetization reversal positions according to a datasequence when recording data; and a compensation value register forstoring compensation values for said compensation means, whereinrecorded data is random data, the number of detection levels of saiddetection means is put at “2”, and each time said compensation valueregister setting is changed, a count value of said counting means,obtained using one or more threshold values in said distinction circuit,is store, and from said count values, a value in said recordcompensation value register at which an error distribution is smallestis calculated, and this compensation value is taken as the optimumcompensation value.
 31. An information recording/reproducing apparatuscomprising: recording and reproducing heads; and a signal processingcircuit operationally connected to said recording and reproducing heads,said signal processing circuit including an equalizer circuit, anamplitude detection circuit, connected to an output of said equalizercircuit, for sequentially detecting amplitudes of an output signal ofsaid equalizer circuit, detection means for receiving said output signalas an input signal thereto and detecting said output signal, an errorcalculating means for calculating an error signal relating to anamplitude error occurring at said detection means from said input signaland an output signal from said detection means, distinction means,having a threshold value set therein, for outputting a count signal whenan error signal is larger than said threshold value, counting means forcounting said count signals, a register for setting a detection level ofsaid detection means, and a register for setting a number of detectionlevels of said detection means; non-volatile storage means, providedindependently of said signal processing circuit, for storing at leastany one of a write current setting value, a sense current setting value,a d.c. offset setting value, coefficient values of said equalizercircuit, and a compensation value of record compensation means, whichare suitable for recording and reproduction on a recording/reproducingmedium; and means for reading at least any one of said setting valuesfrom said non-volatile storage means, and setting said value in saidsignal processing circuit when supplying power to said informationrecording/reproducing apparatus or when selecting a recording orreproducing area of said information recording/reproducing apparatus.32. A signal processing circuit comprising: an equalizer circuit; anamplitude detection circuit, operatively connected to an output of saidequalizer circuit, for sequentially detecting amplitudes of an outputsignal of said equalizer circuit; and error detection means includingdistinction means for receiving said output signal of said equalizer asan input signal thereto, and outputting a count signal in response tosaid input signal larger than a threshold value, counting means forcounting count signals, and register means for setting said thresholdvalue.
 33. A signal processing circuit comprising: an equalizer circuit;an amplitude detection circuit, operatively connected to an output ofsaid equalizer circuit, for sequentially detecting amplitudes of anoutput signal of said equalizer circuit; and error detection meansincluding first distinction means for receiving said output of saidequalizer circuit as an input signal thereto and outputting a firstcount signal in response to said input signal less than a thresholdvalue, first counting means for counting said first count signals,second distinction means for outputting a second count signal inresponse to said input signal larger than a threshold value, secondcounting means for counting said second count signals, count valuecalculating means for subtracting a count value of said second countingmeans from a count value of said first counting means, and means forsetting said threshold value.
 34. A signal processing circuit accordingto claim 33, wherein, of said output signal of said equalizer circuit,that portion of said output signal which excludes signs is used as aninput signal to said error detection means.
 35. A signal processingcircuit according to claim 33, wherein there are provided two modes,including a first mode that, of said output signal of said equalizercircuit, that portion of said output signal which excludes signs is usedas said input signal of said error detection means and a second modethat said output signal including signs is used as said input signal,and a register for switching said two modes is provided.
 36. Aninformation recording/reproducing apparatus, comprising: a head diskassembly; a signal processing circuit connected to said head diskassembly, said signal processing circuit including an equalizer circuit,an amplitude detection circuit, connected to an output of said equalizercircuit, for sequentially detecting amplitudes of an output signal ofsaid equalizer circuit, and an error detection circuit for receivingsaid output signal of said equalizer circuit as an input signal thereto,said error detection circuit including first distinction means foroutputting a first count signal in response to an input signal less thana threshold value, counting means for counting said first count signals,second distinction circuit for outputting a second count signal inresponse to said input signal larger than the threshold value, secondcounting means for counting said second count signals, count valuecalculating means for subtracting a count value of said second countingmeans from a count value of said first counting means, and means forsetting said threshold value; a register switchably setting therein afirst mode in which, of said output signal of said equalizer circuit,that portion of said output signal which excludes signs is used as aninput signal of said error detection means, and a second mode in whichsaid output signal including signs is used said input signal; arecording medium having a plurality of recording/reproducing areas; andnon-volatile storage means, provided independently of said signalprocessing circuit, for storing a set of recording/reproducingparameters optimum for each of said recording/reproducing areas, whereinwhen a recording/reproducing area is selected, a set ofrecording/reproducing parameters optimum for said recording/ reproducingarea is set in said signal processing circuit.
 37. An informationrecording/reproducing apparatus comprising: a head disk assembly; arecorded signal processing circuit connected to said head disk assembly;and a reproduced signal processing circuit connected to said head diskassembly, wherein said recorded signal processing circuit includes apre-coder for generating a pre-coded data sequence by preceding at leasta serial recorded code data sequence, and when recording data, saidpre-code means is reset or preset just before a sync byte indicating astart of data so that a specific data pattern can be recorded as apre-coded data sequence.
 38. An information recording/reproducingapparatus according to claim 37, wherein a recording method is such thata flux reversal of a write current occurs at data “1” and the ongoingwrite current direction is maintained at data “0”, and a recorded codedata sequence corresponding to a sync byte is set such that data beginswith “0” and data “1” does not continue in serial data sequence.
 39. Aninformation recording/reproducing apparatus according to claim 38,wherein a sequence of recorded code data “0” and “1” corresponding tosaid sync byte differs for more than ½ of a byte from a sequence ofrecorded code data “0” and “1” recorded continuously before a sync byte.40. A signal processing circuit having an mixture of an analog signalprocessing block and a digital signal processing block, comprising: alarge scale integrated circuit (LSI) in an at least two-chip structure,including an analog chip which forms at least said analog processingblock and a digital chip which forms at least said digital signalprocessing block; and an equalizer circuit, wherein said digital chipincludes a phase detection circuit, connected to receive output signalof said equalizer circuit, for sequentially detecting phases of saidoutput signal of said equalizer circuit, a first current-output type D/Aconverter circuit for D/A converting an output signal of said phasedetection circuit, an amplitude detection circuit, connected to receivesaid output signal of said equalizer circuit, for sequentially detectingamplitudes of said output signal of said equalizer circuit, a secondcurrent-output type D/A converter circuit for D/A converting an outputsignal of said amplitude detection circuit, and pins having outputs ofsaid first and second D/A converter circuits connected thereto, andwherein said analog chip includes a phase control circuit and anamplitude control circuit having output signals of said first and secondD/A converter circuits supplied respectively thereto.
 41. A signalprocessing circuit having a mixture of an analog signal processing blockand a digital signal processing block, and also having partial responsewaveform equalizing and maximum likelihood decoding functions, saidsignal processing circuit comprising: a large scale integrated circuit(LSI) in an at least two-chip structure, including an analog chip whichforms at least said analog processing block and a digital chip whichforms at least said digital signal processing block, wherein saiddigital chip includes a phase detection circuit and an amplitudedetection circuit, first and second current-output type D/A convertercircuits for respectively D/A converting output signals of said phaseand amplitude detection circuits, and pins having outputs of said firstand second D/A converter circuits connected thereto, and wherein saidanalog chip includes a phase control circuit and an amplitude controlcircuit having output signals of said phase and amplitude detectioncircuits supplied respectively thereto.
 42. A signal processing circuitaccording to claim 41, wherein said signal processing circuit has aTrellis code modulation function in addition to said partial responsewaveform equalizing function and said maximum likelihood decodingfunction.
 43. An information recording/reproducing apparatus comprising:a head disk assembly; and a signal processing circuit electricallyconnected to said head disk assembly, said signal processing circuithaving a mixture of an analog signal processing block and a digitalsignal processing block, including partial response waveform equalizingand maximum likelihood decoding functions, and being formed in a largescale integrated circuit (LSI) of an at least two-chip structure havingan analog chip which forms at least said analog signal processing blockand a digital chip which forms at least said digital signal processingblock, wherein said digital chip includes phase and amplitude detectioncircuits, first and second current-output type D/A converter circuitsfor respectively D/A converting output signals of said phase andamplitude detection circuits, and terminals having outputs of said firstand second D/A converter circuits connected thereto, wherein said analogchip includes a phase control circuit and an amplitude control circuithaving output signals of said phase and amplitude detection circuitssupplied respectively thereto, and wherein a reproduced signal of apre-amplifier for amplifying a signal detected from a recording mediumis input to said analog chip, a digital signal after decoding is outputfrom said digital chip, and a digital signal of data to be written onsaid recording medium is input to said digital chip.